Muhammad Yousaf Ali Khan,Abid Saleem,Asif Nawaz,Nasru Minallah,Rehan Ali Khan,Muneeb Sadat,Zeeshan Najam,Sheeraz Ahmed,



Array binding and allocation,Dynmic random-access memory (DRAM),effective sheduling,empty slots management,memory latency,multi-core processors on chip (MPSoC).,


The modern digital systems especially those dealing with enormous data consumption application are facing a very complicated problem of high latency in these memory access application. Latency seems to be a major hurdle in the performance of modern memory dependent systems as it experiences delay in the processing. This high latency depends upon too many factors especially applications involving memory access operation. Out of these major factors one is of the binding and allocation application. Number of different approaches in the recent past has adopted to optimize the high latency in memory access application. Yet the modern embedded system faces high latency still due to enormous data transfer. In our approach we focus to optimize the latency of modern digital system by dividing the memory into groups. Following by activating, the fourth coming commands in advance in idle slots of different memory modules. The approach is called slag time management. In our algorithm effective distribution of memory into modules activating the later command in advance is followed by the advance dynamic buffers for saving the most frequently access arrays in it.The proposed technique of dividing the memory into modules utilizing the memory management idle slot management in use of advance of dynamic buffers has significantly approved the overall of latency of


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