HIGH PERFORMANCE SR LATCH IN VLSI CIRCUITS USING FINFET 18NM TECHNOLOGY

Authors:

SUDHAKAR ALLURI,

DOI NO:

https://doi.org/10.26782/jmcms.2019.12.00023

Keywords:

Low power,delay,area,FinFET SR Latch,FinFET NAND gate,DSP,VLSI,

Abstract

In present days, low power Very Large Scale Integration (VLSI) circuit assumes a significant job in structuring effective vitality sparing electronic frameworks for rapid execution. In this, low power utilization one of the most significant criteria in different gadgets like cell phones, workstations, High-speed work stations, and so on. FinFETs area unit multi-door transistors that supply higher entry direct management is very little component advancements. They show higher and lower spillage contrasted with the Complementary metal oxide semiconductor planar. As appeared in Figure one, the door is created of a slim balance that associates the availability of the channel on to form the avenue. The avenue is middle between 2 facet entryways on 2 inverse sides. the weather of the door area unit calculable through the entry length, chemical compound thickness, balance dimension, and balance tallness. The activity of the FinFET semiconductor unit is basically similar because of the CMOS planate. In this paper, an SR Latch utilizing eight transistors has been proposed. The proposed SR Latch is planned to utilize the CADENCE EDA apparatus and re-enacted utilizing the Specter Virtuoso at FinFET 18 nm innovation. The proposed outcomes as far as power, area, and delay from table3, table4, table5, and table6.

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