Authors:Partha Mitra,Angsuman Sarkar,
Keywords:Decoupling capacitor,Flower Pollination Algorithm,Multiple Power Supply,Power Distribution Network,System-on-chip,
AbstractDesigning an efficient power distribution network is a major challenge in modern day system-on-chip. During manufacturing, the signal integrity problems such as resistive voltage drop, inductive noise at pad locations and electro-migration may result silicon failures. This paper deals with the analysis of supply noise using multiple power supply and use of decoupling capacitors for reduction of supply noise. In this work flower pollination algorithm has been used for decap estimation so that the supply noise can be reduced significantly and various design parameters remains at its best. The purpose of this work is to reduce the supply noise with effecting the other design parameters of the chip. In this work the supply noise has been reduced upto 70.2% with reduction of 81.6% in power consumption and 17.07 % increment in delay parameters. This approach can be used for any system-on-chip.
I. C. Tirumurti, S. Kundu, S. Sur-Kolay, Y.Chang, “A modeling approach for addressing power supply switching noise related failures of integrated circuits”, Proceedings of Design, Automation and Test in Europe Conference and Exhibition (DATE) pp.: 1078- 1083, 2004.
II. J. A. Strak, H. Tenhunen, “Investigation of timing jitter in NAND and NOR gates induced by power- supply noise”, Proceedings 13th IEEE International Conference on Electronics, Circuits and Systems 2007.
III. K. Shah, “Power Grid Analysis in VLSI Designs”, Dissertation in Master of Science (Engineering),Super Computer Education and Research Centre, Indian Institute of Science Bangalore, 2007.
IV. K. Shimazaki, T. Okumura, “A Minimum Decap Allocation Technique Based on Simultaneous Switching for nano-scale SoC”.Proceedings of IEEE Custom Integrated Circuits Conference, 2009.
V. M. Khellah, D. Khalil, D. Somasekhar, Y. Ismail, T. Karnik, V.De, “Effect of power supply noise on SRAM dynamic stability”, Proceedings of Symposium on VLSI Circuits 2007.
VI. M. Musab, S. Yellampalli, “Study and Implementation of Multi-VDD Power Reduction Technique” Proceedings of IEEE International Conference on Computer Communication and Informatics (ICCCI), pp.: 1-4, 2015.
VII. M. Saint-Laurent, M. Swaminathan, “Impact of power-supply noise on timing in high frequency microprocessors”, IEEE Transactions on Advanced Packaging, Vol.:27, pp.: 135-144, 2004.
VIII. P. Mitra, J. Bhaumik, “Pre-Layout Decap Allocation for Noise suppression and Performance Analysis for 512-Point FFT core”, Proceedings of 2017 Devices for Integrated Circuits (DevIC), pp.: 341-345, 2017.
IX. P. Mitra, J.Bhaumik, “A CAD Approach for Suppression of Power Supply Noise And Performance Analysis of Some Multi-core Processors in Pre-layout Stage”, Microsystem Technologies, Springer, Vol.: 25, Issue: 5, pp.: 1977-1986, 2019.
X. S. A.Tawfik, V. Kursun, “Multi-Vth Conversion circuits For Multi-VDD Systems”, Proceedings of IEEE International Symposium on Circuits and Systems, pp.: 1397-1400, 2007.
XI. S. Ghosh., B.P. De, R. Kar, D. Mandal, A. K. Mal, “Optimal design of a 5.5GHz lowpower highgain CMOS LNA using the Flower Pollination Algorithm”. Journal of Computational Electronics, Springer 2019. DOI: 10.1007/s10825-019-01322-6
XII. S. Pant, “Design and analysis of Power Distribution Networks in VLSI Circuits”, Ph.D Dissertation,University of Michigan, 2008.
XIII. S. Zhao, K. Roy, C.K. Koh, “Decoupling Capacitance Allocation and Its Application to Power-Supply Noise-Aware Flooring”, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems , Vol.: 21, Issue: 1, pp.: 81-92, 2002.
XIV. T. Karim, “On-Chip Power Supply Noise: Scaling, Suppression and Detection”, Ph.D Dissertation, University of Waterloo, 2012.
XV. X.S. Yang, “Flower Pollination Algorithm for Global Optimization”, Lecture Notes In Computer Science, Springer, Vol. 7445, pp.: 240–249, 2012.
XVI. Y. Shi, J. Xiong, C. Liu, L. He,“Efficient Decoupling Capacitance Budgeting Considering Operation and Process Variations”, IEEE Trans. on CAD , Vol.: 27, Issue: 7, pp.: 1253-1263, 2008.