P.Kishore,K.C.Koteswaramma,Y.Chalapathi Rao,



1-bit full adder,Carry Save Adder,Gate Diffusion Input,Power Dissipation,Propagation Delay,


Adders are the fundamental building blocks for any digital processors in VLSI design. Thepropagation delay should be low for high level applications and thus the speed is depends on the propagation delay of the full adders.Hence, the efficientdesign of the full adder is one of the major concerns in fulfilling the requirements of latest applications. As there is lot of research is carrying on full adder designs, still there is a scope of improvement. This paper aimed at design of high performance Carry Save Adder (CSA) using a modified 1-bit full adder. Initially, the basic building blocki.e., a full adder is discussed using existing and proposed Modified Gate Diffusion Input (Modified GDI) techniques. Later, by using this proposed adder the CSA have been designed and compared its performance with respect to speed, Power dissipation and area. All the proposed designs are designed in mentor graphics tools at 90nm technology.


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