Runtime adaptive Dynamic Voltage Frequency Scaling technique for reducing the power consumption in Multi Processor System On Chip


M. Jasmin,S. Philomina,





In VLSI due to recent advancements , there is a need for integration of multiple processors into a single chip. System on chip (Soc) and MPSoc consist of many processors on a single dye. In Soc power dissipation is the most critical factor, which has to be given more importance.Hence power optimization techniques have been proposed.To have an effective analysis on Power optimization ,surveys on various power optimization techniques have been presented. Power dissipation that occurs in digital circuits is mainly due to the logic elements, clocks, memories and other components. To minimize the power dissipation various techniques are analysed to achieve an effective integration of all types of SOCs with increased bandwidth and frequencies Network on chip (NoC) has been later evolved .But NoC consumes more power due to high operating frequencies.So there is a need to reduce power during compilation to increase the performance of the system. Power optimization during run time compilation is alsoexplained.In NOC power is mainly utilized during the data communication between various processing elements. Hence power utilization due to the communication links in the digital circuits is discussed. The methodologies to implement dynamic voltage and frequency scaling (DVFS) in digital design have been discussed. This paper mainly focuses on Various power optimization techniques for reducing the power utilization in network .


I. E.Beigne, F.Clermidey, H.Lhermet,S.Miermont , Y.Thonnart, X.Tran,
A.Valentin, D.Varreau , P.Vivet, X.Popon, and H.Lebreton, “An
asynchronous power aware and adaptive NOC based circuit,” IEEE Journal
of solid-state Circuits, Vol 44 , pp. 1167 – 1177, Apr2009.
II. S.Beulah Hemalatha,T.Vigneshwaran,M.Jasmin “Survey on Energy
efficient Methodologies and architectures of Network-on-Chip”Indian
Journal of Science and Technology,Vol 9(12), pp 1-8,2016.
III. K.Choi, M.Soma, and M. Pedram , “Fine-grained dynamic voltage and
frequency scaling for precise energy and performance tradeoff based
on the ratio of off-chip access to on-chip computation times,” IEEE
Transactions on Computer-Aided Design of Integrated Circuits and
Systems, Vol 24, pp.18-28,Nov2006.
IV. E.Y. Chung, L.Benini,and G.D.Micheli, “Contents provider-assisted
dynamic voltage scaling for low energy multimedia applications,”
Proceedings of the 2002 International Symposium On Low Power Electronics and
Design, ISLPED ’02, Aug.2002,pp. 42-47.
V. X.Chen , Z. Xu, H. Kim, P.Gratz, J.Hu, M.Kishinevsky, and U.Ogras, “Innetwork
monitoring and control policy for DVFS of cmp networks-on-chip
and last level caches”. In Journal ACM Transactions on Design
Automation of Electronic Systems (TODAES) ,Vol 18, pp.43-50, July
VI. T.R.DaRosa, “ Power Consumption Reduction in MPSoCs through DFS”in
Integrated Circuits and System Design (SBCCI), pp 1-6,Sep 2012
VII. S.Das, C.Tokunaga, S.Pant , W.H.Ma,S.Kalaiselvan, K.Lai, D.M. Bull,
D.T.Blaauw, and Razorii “In situ error detection and correction for PVT and SER tolerance”, IEEE Journal of Solid State Circuits, JSSC,Vol
44,pp.32-48,Jan 2009.
VIII. K.Goossens, D.She, A.Milutinovic, and A.Molnos, “Composable Dynamic
Voltage and Frequency Scaling and Power Management for Data flow
Applications”, 13th Euromicro Conference on Digital System
Architecture, Methods and tools,Lille, Sep.2010,pp.107-114 .
IX. C.H.Hsu and W.C. Feng, “Effective dynamic voltage scaling through CPU –
boundedness detection,” inPower-AwareComputer Systems, pp. 135–
X. C.L.Hsu, W.T.Wang, andY.F.Hong, “Frequency-scaling approach for
managing power consumption in NoCs”, EICE Transaction Fundamentals
Electronics Communications and Computer Science, Vol 12, pp. 3580–3583
, Dec2005.
XI. J.Howard,S.Dighe, S.R.Vangal,P.Aserson, S.Kumar, T.Jacob,
K.A.Bowman, J.Howard , J.Tschanz ,V. Erraguntla, N.Borkar ,
V.K.De,and S.Borkor , “A 48-core ia-32 processor in 45 nm CMOS using
on-diemessage-passing and DVFS for performance and power
scaling,” IEEE Journal of Solid-State Circuits, Vol 46,pp. 173-183,
XII. E.J. Kim, K.H.Yum, andG.M.Link, N.Vijaykrishnan, M.Kandemir, M.J.Irwin,
M.Yousif, and C.R.Das, “Energy optimization techniques in cluster
interconnects”, in: ISLPED ’03:Proceedings of the 2003 International
Symposium on Low Power Electronics and Design, ACM, NY, USA, IEEE
Published, , Aug 2003,pp. 459–464.
XII1 J.Kimand M.A.Horowitz, “Adaptive supply serial links with sub-1v operation
and per-pin clock recovery”, IEEE Journal Of Solid-State Circuits, Vol
XIV. J.Luo, J.K.Jha, and L.S.Peh, “Simultaneous dynamic voltage scaling of
processors and communication links inreal-time distributed embedded
systems” IEEE transactions on VLSI Systems,Very Large Scale Integration,
Vol15,pp.427–437,Apr 2007.
XV. F.Li, G.Chen, and M.Kandemir, “Compiler-directed voltage scaling on
communication links for reducing power consumption” in: ICCAD ’05:
Proceedings of the 2005 IEEE/ACM International Conference on Computer-
Aided Design, IEEE Computer Society,IEEE Published,May.2005,pp. 456–
XVI. J. Lee, B.G. Nam,and H.G.Yoo, “Dynamic Voltage and Frequency Scaling DVFS) Scheme for Multi-Domains Power Management” in Solid State
Circuits Conference, ASSCC’07,IEEE Published ,Jeju, , Nov.2007,pp.360-
XVII. G. Liang, and A.Jantsch “Adaptive power management for the on-chip
communication network” in Proc. 9th Euromicro Conference on Digital
System Design: Architectures, Methods and tools,DSD’06 ,IEEE
XVIII. S.M.Martin, K.Flautner, T.Mudge, and D.Blaauw, “Combined dynamic
voltage scaling and adaptive body biasing for lower power microprocessors
under dynamic workloads,” in Proceedings of the International Conference ,
Computer-Aided Design,ICCAD’02IEEE Published, Nov.2002,pp. 721–725.
XIX. A.K.Mishra, R.Das, S.Eachempati, and R.Iyer,“A case for dynamic
frequency tuning in on-chip networks”. In 42nd Annual IEEE/ACM
International Symposium on Microarchitecture, Micro-42,IEEE
Published, Dec2009 , pp. 292–303
XX. L.Shang, L.Peh,and N.K.Jha, “Power-efficient interconnection networks:
dynamic voltage scaling with links” IEEE Computer Architecture Letters, Vol
1, pp.6 ,Dec2002.
XXI. V.Soteriou, N.Eisley,and L.S.Peh, “Software-directed power-aware
interconnection networks”, ACM Transactions architecture Code
Optimization, Vol 4, pp.5,Mar 2007.
XXII L.Shang, L.S.Peh, and N.K. Jha, “ Dynamic voltage scaling with links for
power optimization of interconnection networks” in Proceedings of the 9th
International Symposium on High-Performance Computer Architecture,
HPCA’03, IEEE Published, pp. 91–102,Feb 2003.
XXIII D.Shin andJ.Kim, “Power-aware communication optimization for networkson-
chips with voltage scalable links” in:CODES ISSS ’04: Proceedings of the
International Conference on Hardware/Software Code sign and
System Synthesis, IEEE Computer Society, Washington DC, USA, IEEE
Published,Sep 2004,pp. 170–175.
XXIV S.W.Son, K.Malkowski, G.Chen, and M.Kandemir , “Integrated link/CPU
voltage scaling for reducing energyconsumption of parallel sparse matrix
applications”. In 20th International Parallel and DistributingSymposium
IPDPS’06, Apr2006,pp. 339.
XXV V. Soteriou and L.S.Peh, “Dynamic Power Management for Power
Optimization of Interconnection Networks Using On/Off Links”. In Proceedings 11th Symposium on High Performance Interconnects,
XXVI G.Wei, J.Kim, D.Liu, S.Sidiropoulos, and M.A.Horowitz, “A variablefrequency
parallel I/O interface with adaptivepower-supply regulation”,
IEEE Journal of Solid State Circuits,,Vol 35, pp.1600–1610,Nov2000.
[XXVII] Quintin Fettes, Mark Clark, Razvan Bunescu, Avinash Karanth, “Dynamic
Voltage and Frequency Scaling in NoCs with Supervised and
Reinforcement Learning Techniques” in IEEE Transactions on
Computers,January 2018
[XXVIII] A.W.Yin, L.Guang, E. Nigussie, and P. Liljeberg “Architectural
Exploration of Per-Core DVFS for Energy-Constrained On-Chip
Networks” 12th Euromicro Conference on Digital System
Architecture,Methods and tools , DSD’09 IEEE Published, Dubrovnik ,
Aug.2009,pp 141-146.


View | Download