High Performance Matrix Multiplication based on Xilinx Virtex FPGA


S. Arulselvi,B. Karthik,M. Jasmin,Balaji S,




Parallel processing,Pipelining,Matrix multiplier,Clock timing,design area,


Concurrent data processing is used is used to rise the computational speed of computer system in parallel processing. This is implemented by pipeline processing. In this article we offered design of a Pipelined Matrix Multiplier and its results is stored in matrix. We present design and stimulate a functional Pipelined Matrix Multiplier Unit. By which we can learn about the working of Pipelined Matrix Multiplier and how pipelining works. We also get the knowledge of clock timing and learn to make a timing critical design. In this Pipelined Matrix Multiplier Unit design we use design compiler, which is a module of Synopsys tools that uses lsi_10k library and BCCOM method to synthesis the design and simulate the design through VCS compiler.


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