A Novel Architecture for Low Power Equiripple Half-Band FIR Filter using GDI Based Dual Edge Triggered Flip-Flop


Biswarup Mukherjee,Aniruddha Ghosal,




Half-band FIR filter,Dual Edge Triggered Flip Flop (DETFF), GDI ,Multiplexer, Low power VLSI ,


In this paper, a technique for implementing low-power equiripple half-band FIR filter using GDI based Dual Edge Triggered Flip Flop (DETFF) is introduced. Dual edge triggered flip flops has many advantages in low power VLSI compared to SETFF. The Proposed low power FIR filter using DETFF is implemented and compared with conventional design at same simulation conditions. CAD tool based simulation and comparison between proposed design with the conventional design shows that the proposed design reduces power dissipation by 32% reducing the no. of transistors used while keeping the same data rate.


I.A.Liacha, A. K. Oudjida, F. Ferguene, M. Bakiri, M. L. Berrandjia, “Design of high-speed, low-power, and area-efficient FIR filters”, IET Circuits, Devices & Systems, Vol.: 12, Issue: 1, 2018

II.A. Morgenshtein, A. Fish and Israel A. Wagner, “Gate-Diffusion Input (GDI): A Power-Efficient Method for Digital Combinatorial Circuits”, IEEE Transaction on VLSI Systems, Vol. 10 issue 5, pp. 566-581, Oct. 2002

III.A. Ogata, N. Aikawa; M. Sato,”A design method of low delay FIR bandpass filters”, IEEE International Symposium onCircuits and Systems Emerging Technologies for the 21st Century, Volume: 1 Pages: 92 -95, 2000IV.B. Mukherjee, A. Ghosal, “Design & Study of a Low Power High Speed Full Adder Using GDI Multiplexer”, IEEE 2nd International Conference on Recent Trends in Information Systems (ReTIS),pp:465-470, 2015

V.B. Mukherjee, B. Roy, A. Biswas, A. Ghosal, “Design of a Low Power 4×4 Multiplier Based on Five Transistor (5-T) Half Adder, Eight Transistor (8-T) Full Adder & Two Transistor (2-T) AND Gate”, Third International Conference on Computer, Communication, Control and Information Technology (C3IT), 2015

VI.B. Yuan; Y. Wang, “High-Accuracy FIR Filter Design Using Stochastic Computing”, 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)pp: 128 –133, 2016

VII.G. N. Jyothi, S. SriDevi, “Distributed arithmetic architectures for FIR filters-A comparative review”, International Conference on Wireless Communications, Signal Processing and Networking (WiSPNET), pp. 2684-2690, 2017

VIII.G. Singh and C. Goel, “Design of Low Power andEfficient Carry Select Adder Using 3-T XOR Gate”, Advances in Electronics, Article ID 564613, 2014

IX.I. H. H. Jørgensen, P. Pracny, E. Bruun, “Hardware-Efficient Implementation of Half-Band IIR Filter for Interpolation and Decimation”, IEEE Transactions on Circuits and Systems II: Express Briefs, Volume: 60, Issue: 12, Pages: 892 -896, 2013

X.J. Chen; J. Tan, C. Chang, F. Feng, “A New Cost-Aware Sensitivity-Driven Algorithm for the Design of FIR Filters”, IEEE Transactions on Circuits and Systems I, Volume: 64, Issue: 6 pp: 1588 -1598, 2017

XI.J. Fadavi-Ardekani, “M*N Booth encoded multiplier generator using optimized Wallace trees”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume: 1, Issue: 2 pp: 120 -125, 1993

XII.Liang Li, Xingfa Huang, Zhou Yu, “A full custom half-band filter used for sigma-delta ADC”, International Conference on Anti-Counterfeiting, Security and Identification, pp-116-119, 2010

XIII.Nitin Kumar Saini , Kamal K. Kashyap; “Low power dual edge triggered flip-flop”, International Conference on Signal Propagation and Computer Technology (ICSPCT), 2014

XIV.P. P. Vaidyanathan, “Design and implementation of digital FIR filters,” in Handbook of Digital Signal Processing Engineering Applications, D. F. Elliott, Ed., pp. 55–172, Academic Press,London, UK, 1987.

XV.P. Zahradnik, “Equiripple Approximation of Low-pass FIR Filters Equiripple Approximation of Low-pass FIR Filters”,IEEE Transactions on Circuits and Systems II: Express Briefs, Issue: 99,pp. 1-5, 2017

XVI.P. Zhao, J. McNeely, P. Golconda,M. A. Bayoumi, R. A. Barcenas, W. Kuang, ” Low-Power Clock Branch Sharing Double-Edge Triggered Flip-Flop”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol.: 15, Issue: 3,pp: 338 -345, 2007

XVII.R. Kubasek, Z. Smekal, E. Gescheidtova, K.Bartusek, “Design of Two-channel Half-band Bank of Digital Filters using Optimization Methods”, International Conference on Networking, International Conference on Systems and International Conference on Mobile Communications and Learning Technologies, page: 151, 2006

XVIII.S. Archana, G. Durga, “Design of low power and high speed ripple carry adder”, International Conference on Communication and Signal pocessing, pp: 939 -943, 2014

XIX.S. K. Mitra and J. F. Kaiser, Handbook for Digital Signal Processing. New York,NY, USA: Wiley, 1993.

XX.S. Samadi, A. Nishihara, H. Iwakura, “Universal maximally flat low pass FIR systems”, IEEE Transactions on Signal Processing Vol: 48, Issue: 7,pp: 1956 -1964,2000

XXI.Wen Bin Ye, Xin Lou, Ya Jun Yu, “Design of Low-Power Multiplierless Linear-Phase FIR Filters” , IEEE Access, Volume: 5,pp: 23466 -23472,2017

XXII.X. Zhang, K. Intosume, and T. Yoshikawa, “Design of low delay FIR half-band filters with arbitrary flatness and its application to filter banks,” Electron. Comm. Jpn 3, vol. 8, no. 10, pp. 1–9, 2000

Author(s): Biswarup Mukherjee, Aniruddha Ghosal View Download