Design of 5-Stage Ring Oscillator using Mentor Graphics 130nm Technology


Kumaraswamy Gajula,



Layout Vs Schematic (LVS),Inverter,Oscillator,Mentor Graphics,


The design of layout and source VLSI by way of low design rules is a difficult assignment before fabricating required device. A RF integrated circuit contains extensive applications is Ring Oscillator (RO). Current article focus a novel method of design, where a ring oscillator (RO) is simulated with Layout versus Source(LVS) report for physical verification using mentor graphics with Pyxis schematic, ELDOsimulation, EzWaves, Pyxis Layout and Calibre tools. Here RO circuit is designed with inverters of 5 stages operating at 9 GHz with the boundaries obligatory by gdk Generic 13 library. Simulated results, schematic, layout with LVS reports are presented here to verify design of RO with Mentor graphics EDA back end tool in efficient manner compared to Cadence.


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