A novel high speed 0.17mw pseudo divideBy 32/33 dual modulus prescaler


Uma Nirmal,V.K. Jain,




2/3 prescaler, 4/5 prescaler, divide by 32/33 prescalers, I –ETSPC,Sleepy Keeper Approach,


n this paper, we implement divide by 32/33 dual modulus prescaler(DMP) using I-ETSPC based: divide by 2/3prescaler and divide by 4/5 by prescaler at 180nm CMOS technology. The divide by 32/33 dual modulus prescaler using 2/3 prescaler and 4/5 prescaler consumes 1.03mW and 0.85mW power from 1.2V and 1V respectively. To further improve speed and reduce design complexity with low power consumption a pseudo divide by 32/33 dual modulus prescaler is proposed. According to simulation results the pseudo divide by 32/33 dual modulus prescaler reaches a maximum 9.2 GHz working frequency at 1V with a 0.17mw power consumption. This prescaler is compared with Proposed I-ETSPC based divide by 32/33 using 2/3 and 4/5 prescalers and also with other recently published divide by 32/33 prescalers.Compared with previous conventional divide by 32/33 DMPs, this design contains fewer transistor numbers.


I.C. Lee, L. C. Cho and S. I. Liu, “A 44GHz Dual-Modulus Divide-by-4/5 Prescaler in 90nm CMOS Technology,” IEEE Custom Integrated Circuits Conference (CICC ’06),San Jose, CA, pp. 397-400, 2006.

II.F. P. H. Miranda, J. Navarro and W. A. M. Van Noije, “ A 4 GHz Dual Modulus Divider-by 32/33 Prescaler in 0.35μm CMOS Technology” In Proc. of the 17th annual symposium on Integrated circuits and system design(SBCCI‟04), Pernanbuco, Brazil, pp. 94-99, Sept. 7-11, 2004.

III.F. P. H. Miranda, J. Navarro and W. A. M. Van Noije,“A 4.1 GHz Prescaler Using Double Data Throughput E-TSPC Structures,” In Proc. of the 20th annual symposium on Integrated circuits and system design(SBCCI‟07),Rio de Janeiro, Brazil, pp. 123-127, Sept. 3-6, 2007.

IV.J. N. Soares, Jr. and W. A. M. Van Noije, “A 1.6-GHz dual modulus prescaler using the extended true-single-phase-clock CMOS circuit technique (E-TSPC),” IEEE J. Solid-State Circuits, vol. 34, no. 1, pp. 97–102, Jan. 1999.

V.J.C. Park, V. J. Mooney, P. Pfeiffenberger, “Sleepy Stack Reduction of Leakage Power”,Proceeding of the International Workshop on Power and Timing Modeling Optimization and Simulation, pp. 148-158, September 2004.

VI.J. Wu, et al.: “A low-power high-speed true single phase clock divide-by-2/3 prescaler,” IEICE Electron. Express10 (2013) 20120913 (DOI: 10.1587/elex. 10.20120913).

VII.J. Navarro, and G. C. Martins, “Design of High Speed Digital Circuits with E-TSPC Cell Library,” In Proc. of the 24th symposium on Integrated circuits and systems design(SBCCI ’11), João Pessoa, Brazil, pp. 167-172, Aug. 30–Sept. 2, 2011 .

VIII.M. V. Krishna, M. A. Do, K. S. Yeo, C. C. Boon, and W. M. Lim, “Design and analysis of ultra-low power true single phase clock CMOS2/3 prescaler,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 1, pp. 72–82, Jan. 2010.

IX.R Jain, U Nirmal et al “Design and Optimization of Pseudo-NMOS basedImproved extended True Single-Phase Clock Technique low-Power Prescaler”, International Conference on Soft Computing,Intelligent Systems and Applications, April 8-9, 2016, Bangalore, India.

X.R. Jain, U. Nirmal et al., “Low Voltage Low Power 4/5 Dual Modulus Prescaler in 180nm CMOS Technology”, International Conference on Research Advances in Integrated Navigation Systems(RAINS -2016), May 6-7, 2016.

XI.S. Bhargava, U. Nirmal, “AUnified Approach in the Analysis of Prescalers and Dual Modulus Prescalers for low-power systems”International Journal of Applied Engineering Research ISSN 0973-4562 Volume 12, Number 12 (2017) pp. 3042-3048.

XII.S. Pellerano , S. Levantino , C. Samori , and A. L. Lacaita, “ A 13.5-mW 5-GHz Frequency Synthesizer with dynamic-logic frequency divider,” IEEE J. Solid-State Circuits, vol. 39, no. 2, pp. 378–383, Feb. 2004.

XIII.Song Jia, Shilin Yan et al, “Low-power, high-speed dual modulus prescaler based on branch-merged true single-phase clocked scheme” ELECTRONICS LETTERS,Vol. 51 No. 6 pp. 464–465, March 2015.

XIV.W.-H. Chen and B. Jung, “High-speed low-power true single-phase clock dual-modulus prescalers,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 58, no. 3, pp. 144 –148, March 2011.

XV.W Jiang et. Al., “A low-power high-speed true single-phase clock-based divide-by-2/3 prescaler” IEICE Electronics Express, Vol 14, No. 1, 1 –6, 2017.

XVI.Xincun Ji et. Al., “ A 2.4 GHz fractional-N PLL with a low power true single phase clock prescaler ” IEICE Electronics Express, Vol 14, No. 8, 1 –8, 2017.

XVII.X.P. Yu, M.A. Do, W. M. Lim, K. S. Yeo, and J. G. Ma, “Design and optimization of the extended true single-phase clock-based prescaler,” IEEE Trans. Microwave Theory Tech., vol. 54, no. 11, pp. 3828–3835, Nov. 2006.

XVIII.Z. Deng and A. Niknejad, “The speed-power trade-off in the design of CMOS true-single-phase-clock dividers,” IEEE Journal of Solid-State Circuits, vol. 45, no. 11, pp. 2457 –2465, Nov. 2010.

Author(s): Uma Nirmal, V.K. Jain View Download