Real Concern to High Speed VLSI Design for Interconnect Scaling


B. Karthik,M. Jasmin,S. Arulselvi,M. Sriram,



MOS,High Speed VLSI,Interconnect Scaling,


Scaling the MOS interconnection line widths, improves the layout density, but the intrinsic propagation delays along maximum length lines are becoming significant and that the coupling between adjacent lines due to ever shrinking separation is also increasing to a noticeable level. In this paper we show the effects of the classical scaling on the effective delay and the coupling capacitance.


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