Partha Mitra,Angsuman Sarkar,



Computer Aided Design (CAD),White Space (WS),System-on-chip (SoC),Power Distribution Network (PDN),Decoupling capacitor (decap),


This paper deals with accurate decoupling capacitance estimation which is commonly used for suppression of power supply noise in modern day system-on-chip. Supply noise is a major issue needs to be addressed for proper functioning which may lead to logic failure in digital integrated circuit. Capacitors directly effects the power consumption and delay parameters and hence the overall performance of integrated circuits.  In this work design verification has been done between the pre-layout stage and post-layout stage. Simulation results show that the difference in results between pre-layout and post-layout stages is marginal. This early detection of errors can be helpful for the designers in the latter stages of the system design. This CAD flow can also be used on any system-on-chip design.


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