Authors:
N. Vinod Kumar,F. Vincy Lloyd,DOI NO:
https://doi.org/10.26782/jmcms.2026.07.00002Keywords:
m-GDI,FinFET,ALU,IoT Processors. Nanoscale Technology.,Abstract
Arithmetic Logic Units (ALUs) play a crucial role in contemporary digital systems; yet, the total performance of processors is greatly affected by factors such as power consumption, propagation delay, silicon size, and energy efficiency. To accomplish high performance with low power consumption, this study suggests an ALU that is based on modified Gate Diffusion Input (m-GDI) FinFETs and is built utilising 18-nm technology. For the sake of objectivity, we used standard scaling techniques to standardise previously published ALU architectures across technology nodes to an 18-nm equivalent. Compared to current ALUs based on CMOS (Complementary Metal Oxide Semiconductor), GDI (Gate Diffusion Input), and FinFET (Fin Field-Effect Transistor), the proposed design routinely achieves better results after normalisation. In comparison to previous designs, the proposed layout for the 1-bit ALU may cut power consumption by as much as 42.8%, propagation delay by as much as 53.0%, silicon area by as much as 11.3%, and the Power-Delay Product (PDP) by as much as 76.2%. Similarly, the 8-bit ALU improves power, delay, area, and PDP by 8.4%, 19.0%, 22.2%, and 17.8%, respectively, whereas the Proposed4-bit ALU reduces power by 21.9%, latency by 7.1%, area by 48.5%, and PDP by 73.7% using the same process. With a power consumption of 13.28 µW, a latency of 624 ps, an area of 65.92 µm², and competitive power consumption per bit, the Proposed16-bit ALU still shows outstanding scalability. These findings add credence to the idea that next-generation very large scale integration (VLSI) applications may benefit from building small, high-performance, energy-efficient ALUs by combining m-GDI logic with FinFET technology.Refference:
I. Alexander Fish, A. Morgenshtein, Arkadiy, , and Israel A. Wagner. "Gate-diffusion input (GDI)-a technique for low power design of digital circuits: analysis and characterization." 2002 IEEE International symposium on circuits and systems. Proceedings (Cat. No. 02CH37353). Vol. 1. IEEE, 2002. 10.1109/ISCAS.2002.1009881
II. Aminul, A. Islam, Md. Hasan, and Md. MonirulHasan.“Design of Energy Efficient Full Adder Using GDI Technique in Nanoscale Technology.” Integration, the VLSI Journal, vol. 54, pp. 56–64. 10.1016/j.vlsi.2016.03.001
III. Aminul, A. Islam, and Md. Monirul Hasan. “Leakage-Aware Low-Power Full Adder Design Using GDI Technique.” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 59, no. 6, 2012, pp. 362–366. 10.1109/TCSII.2012.2196175
IV. Anitesh, A. Sharma and Ravi Tiwari. "Low power 8-bit ALU design using full adder and multiplexer." 2016 International Conference on Wireless Communications, Signal Processing and Networking (WiSPNET). IEEE, 2016. 10.1109/WiSPNET.2016.7566525
V. Ankit, A. Mishra and Shyam Akashe. “Design of Low Power 8-Bit ALU Using Transmission Gate and GDI Technique.” AEÜ – International Journal of Electronics and Communications, vol. 83, 2018, pp. 218–226. 10.1016/j.aeue.2017.10.040
VI. Ahmed, Mahmoud Aymen, and M. A. Abdelghany. "Low power 4-bit arithmetic logic unit using full-swing GDI technique." 2018 International Conference on Innovative Trends in Computer Engineering (ITCE). IEEE, 2018. 10.1109/ITCE.2018.8316623
VII. Alluri, A. Navaneetha and Kalagadda Bikshalu. "Reliability analysis of FinFET based high performance circuits." Electronics 12.6 (2023): 1407. 10.3390/electronics12061407
VIII. Anand, Shubham, and S. Indu. "A low power and high speed 8-bit ALU design using 17T full adder." 2020 7th International Conference on Signal Processing and Integrated Networks (SPIN). IEEE, 2020. 10.1109/SPIN48934.2020.9070844
IX. D. Shaik and S. K. S. Gollapudi, “Analogy of Distinct Constructions FinFET GDI Full Adder,” International Journal of Intelligent Systems and Applications in Engineering, vol. 11, no. 1, 2023. https://www.ijisae.org/index.php/IJISAE/article/view/2484
X. Gautam, Nayan. "A comparative analysis of 8-bit novel adder architecture design using traditional cmos and m-gdi technique." 2019 International Conference on Communication and Electronics Systems (ICCES). IEEE, 2019. 10.1109/ICCES45898.2019.9002573
XI. Jean-Pierre, Colinge "Multiple-gate soi mosfets." Solid-state electronics 48.6 (2004): 897-905.Colinge, Jean-Pierre. "Multiple-gate soi mosfets." Solid-state electronics 48.6 (2004): 897-905.
10.1016/j.sse.2003.12.020
XII. Jaan Diwan, A. Agrawal, and N. Gajjar, “A Power-Efficient 32-Bit ALU Using 16-nm FinFET Technology Based NCL Standard Cells for Asynchronous VLSI Systems,”
International Journal of Environmental Sciences, vol. 11, no. 11, 2025. 10.64252/386xw282
XIII. Kauschick ,Roy, Saibal Mukhopadhyay, and Hamid Mahmoodi-Meimand. "Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits." Proceedings of the IEEE 91.2 (2003): 305-327. 10.1109/JPROC.2002.808156
XIV. Kumar, Manish, Md Anwar Hussain, and L. L. K. Singh. "Design of a low power high speed ALU in 45nm using GDI technique and its performance comparison." International Conference on Advances in Communication, Network, and Computing. Berlin, Heidelberg: Springer Berlin Heidelberg, 2011.
10.1007/978-3-642-19542-6_87
XV. MNG Prasad, K. Prasad Babu, Dr. K.E. Sreenivasa Murthy, Simulation of Optimized Low power 4-bit Processor using 32nm technology/ International Journal of Applied Engineering & Technology, ISSN: 2633-4828 Vol. 6 No.1, January, 2024, Pg.No 1345-1370. https://romanpub.com/resources/ijaet20v6-1-2024-135.pdf
XVI. Md Anwar Hussain, and L. L. K. Singh. "Design of a low power high speed ALU in 45nm using GDI technique and its performance comparison." International Conference on Advances in Communication, Network, and Computing. Berlin, Heidelberg: Springer Berlin Heidelberg, 2011. 10.1007/978-3-642-19542-6_87
XVII. M. Subi stalin, N., et al. "ALUSGDI: Low power arithmetic logic unit based sliced processor using GDI and MGDI." Measurement: Sensors 28 (2023): 100842. 10.1016/j.measen.2023.100842
XVIII. P. K. Dutta and D. K. Roy, “Design and analysis of low power ALU using GDI technique,” Int. J. Electronics, vol. 104, no. 12, pp. 2142–2156, 2017. 10.1080/00207217.2017.1341085
XIX. R. Gullapally, N. S. S. Reddy, and P. Chandra Sekhar, “Design and Analysis of Low-Power VLSI SRAM Cell Using CMOS, FinFET and GNRFET Technologies,” International Journal of ntelligent Systems and Applications in Engineering, vol. 11, no. 3, 2023.
https://ijisae.org/index.php/IJISAE/article/view/3349
XX. Reto, Zimmermann, , and Wolfgang Fichtner. "Low-power logic styles: CMOS versus pass-transistor logic." IEEE journal of solid-state circuits 32.7 (1997): 1079-1090.Zimmermann, Reto, and Wolfgang Fichtner. "Low-power logic styles: CMOS versus pass-transistor logic." IEEE journal of solid-state circuits 32.7 (1997): 1079-1090. 10.1109/4.597298
XXI. Suresh, Sujit, Akarsha Ram, and Prachi Sharma. "Low Power Design Analysis of ALU Using FinFET." 2025 3rd International Conference on Device Intelligence, Computing and Communication Technologies (DICCT). IEEE, 2025. 10.1109/DICCT64131.2025.10986604
XXII. Sankaran Sujatha, Narasimha et al., Agnello, P., et al. "High performance 45-nm SOI technology with enhanced strain, porous low-k BEOL, and immersion lithography." 2006 International Electron Devices Meeting. IEEE, 2006. 10.1109/IEDM.2006.346879
XXIII. Shin’ichiro, Mutoh, et al. "1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS." IEEE Journal of Solid-state circuits 30.8 (1995): 847-854. Mutoh, Shin'ichiro, et al. "1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS." IEEE Journal of Solid-state circuits 30.8 (1995): 847-854. 10.1109/4.400426
XXIV. Sukhreet, Rita Mahajan, and Deepak Bagai. "Power-Optimized 4-Bit Full Adder Using GDI and Adiabatic Logic in FinFET Technology." Advanced Engineering Sciences 57.2 (2025): 31-43. https://advancedengineeringscience.com/index.php/aes/article/view/210
XXV. S. Lodhi, H. Yadav, and R. Patel, “Optimization-Enhanced
Low-Power ALU Design Using Clock Gating and Power Gating,”International Journal for Research in Applied Science and Engineering Technology, 2025.
https://www.ijraset.com/research-paper/o-alu-an-optimization-enhanced-low-power-alu-design
XXVI. Suresh, Sujit, Akarsha Ram, and Prachi Sharma. "Low Power Design Analysis of ALU Using FinFET." 2025 3rd International Conference on Device Intelligence, Computing and Communication Technologies (DICCT). IEEE, 2025. 10.1109/DICCT64131.2025.10986604
XXVII. Sarkar, Shubham, et al. "8-bit ALU design using m-GDI technique." 2020 4th International Conference on Trends in Electronics and Informatics (ICOEI)(48184). IEEE, 2020. 10.1109/ICOEI48184.2020.9142881
XXVIII. Rani, T. Esther, and Rameshwar Rao. "AREA and power optimized multipliers with minimum leakage." 2011 3rd International Conference on Electronics Computer Technology. Vol. 3. IEEE, 2011.. 10.1109/ICECTECH.2011.5941755
XXIX. VShylaja and K. Ezhilarasan, “Design and Performance Efficiency Analysis of a Low-Power 4-bit Arithmetic Logic Unit,” Journal of Electrical Systems, vol. 20, no. 10, 2024. https://journal.esrgroups.org/jes
XXX. Yuan , Taur "CMOS design near the limit of scaling." IBM Journal of Research and Development 46.2.3 (2002): 213-222. 10.1147/rd.462.0213
XXXI. Yuan. Taur, and Tak H. Ning. Fundamentals of modern VLSI devices. Cambridge university press, 2022.
https://books.google.co.in/books?hl=en&lr=&id=cbhIEAAAQBAJ&oi=fnd&pg=PR13&dq=XXX.%09Y.+Taur+and+T.+H.+Ning,+Fundamentals+of+Modern+VLSI+Devices.+Cambridge,+U.K.:+Cambridge+Univ.+Press,+2013.&ots=MbjmvEGtO6&sig=Z93mugfl5uPoqb3sYEovsYw_wiY&redir_esc=y#v=onepage&q&f=false
XXXII. Yadav, Ashish Kumar, Bhavana P. Shrivatava, and Ajay Kumar Dadoriya. "Low power high speed 1-bit full adder circuit design at 45nm CMOS technology." 2017 International Conference on Recent Innovations in Signal processing and Embedded Systems (RISE). IEEE, 2017. 10.1109/RISE.2017.8378203