Authors:
D. V. N. Bharathi,Bala Sindhuri Kandula,Gangula Manikanta,B. Jagadeesh Babu,Subhashini Tata,Kosaraju Swathi,DOI NO:
https://doi.org/10.26782/jmcms.2026.07.00015Keywords:
Iterative approximate floating-point multiplier (IAFPM),IEEE-754 floating-point arithmetic,image multiplication,partial product encoding,error-tolerant image processing,low-power VLSI design,multimedia image processing applications,Abstract
Multiplier efficiency is very significant in image processing and multimedia applications, which involve numerous floating-point multiplications. Although IEEE-754 multipliers are more precise, they also require more power, hardware, and time, which are not suitable for low-power and real-time systems. Simple control logic, partial-product encoding, and error correction are methods used in approximate floating-point multipliers to enhance efficiency. They consume less hardware and power, and still provide acceptable image quality compared to their more exact counterparts, the multipliers. Therefore, they can be used in image processing applications that require error tolerance.Refference:
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